View STCH01_8102037.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. august 2014 docid026783 rev 2 1/58 STCH01 advanced multi-mode power management controller for zero no-load power consumption datasheet - preliminary data features ? cv/cc regulation with or without optocoupler (opto or optoless version respectively) ? burst mode operation at no load, with wake-up from secondary side (optoless version) ? zero power consumption in no load condition (optoless version) with excellent dynamic load transient ? internal high voltage startup ? ovp dedicated pin with sensing from auxiliary winding of transformer ? dedicated pin for protection purpose (prot pin with latched or autorestart option) ? second level ocp (transformer saturation or output rectifier short-circuit) ? online digital trimming for the highest end product accuracy ? intelligent frequency jitter for emi suppression ? low v dd supply voltage operation ? two avalanche rated internal power mosfets applications ? adapter/plug-in charger: mobile phone, tablet, camcorder, shaver, emergency light, etc. description the STCH01device is a high voltage primary switcher intended for operating directly from the rectified mains with minimum external parts. housed in a compact so16n package,STCH01 embeds controller and two dedicated power sections in a unique full integrated solution. the device allows to implement power supplies with extremely low consumption during no-load assuring excellent dynamic load transition response without optocoupler. the converter utilizes two operating modes: forced commutation mode: performed by a high- performance qr pwm controller and a low-side (ls) power mosfet, to serve the purpose of power storage and power control. self commutation mode: performed by an integrated proprietary scheme and a high-side (hs) mosfet, to serve the purpose of resonant power release to the load. : so16n table 1. device summary tube tape and reel version STCH01 STCH01tr optoless and autorestart STCH01l STCH01ltr optoless and latched STCH01nw STCH01nwtr optoless and autorestart STCH01lnw STCH01lnwtr optoless and latched www.st.com
contents STCH01 2/58 docid026783 rev 2 contents 1 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin functions and typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 typical application - optoless version . . . . . . . . . . . . . . . . . . . . . . . 16 7 typical application - opto version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 low-side power section and gate driver . . . . . . . . . . . . . . . . . . . . . 19 8.2 high-side power section and resonant frequency control . . . . . . . . 20 8.3 high voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.4 zero current detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.5 constant voltage regulation (optoless version) . . . . . . . . . . . . . . . . . 24 8.6 constant voltage regulation (opto version) . . . . . . . . . . . . . . . . . . . . . . 25 8.7 constant current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.8 voltage feed-forward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.9 burst mode operation (optoless version) . . . . . . . . . . . . . . . . . . . . . . 30 8.10 burst mode operation (opto version) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.11 frequency jitter for emi reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.12 ovp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.13 hiccup mode ocp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.14 generic protection pin (prot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.15 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 online trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
docid026783 rev 2 3/58 STCH01 contents 58 9.2 device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3 device commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 data strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.4 emulation commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.5 emulate v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.6 emulate g i * v cref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.7 emulate r ff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.8 emulate ipk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.9 read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.9.1 read v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.9.2 read g i * v cref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.9.3 read r ff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.9.4 read ipk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.10 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.11 reset volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.12 write nvm (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.13 multiplexed scl and sda inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
device description STCH01 4/58 docid026783 rev 2 1 device description the device implements a current-mode control specifically designed for quasi-resonant flyback converters operating with valley switching , available in two versions: optoloess and opto. the optoless version is capable of providing constant output voltage (cv) regulation and constant output current (cc) regulation, using primary-sensing feedback. this eliminates the need for the optocoupler, the secondary voltage reference as well as the current sensor, still maintaining quite accurate regulation. the opto version uses a standard secondary side cv regulation with an optocoupler, while cc regulation is still performed with the primary side sensing. quasi-resonant operation is achieved by means of a transformer demagnetization sensing input that triggers the ls mosfet turn-on. the same input is dedicated also to output voltage monitoring, to perform cv regulation, and input voltage monitoring, to achieve mains independent cc regulation (line voltage feed-forward). a blanking time after the turn-on is inserted to allow for valley-skipping operation at a medium-light load, assuring in this way high-efficiency over wide range of the output load. at a very light load, the device enters a controlled burst mode operation that, along with the built-in high voltage start-up circuit and the low operating current of the device, helps minimize the residual input consumption. with the optoless version, in no load, light load conditions, the controller stops operating (entering a very low consumption state) and remains waiting for a wake-up signal pulse (on zcd pin) from the secondary side. during cc regulation, where the flyback voltage generated by the auxiliary winding drops and may be not enough to supply the internal circuits, the chip is able to power itself directly from the rectified mains through the high voltage start-up circuit. during the burst mode operation the self-supply feature is disabled (due to very stringent no load consumption requirement), and the v dd supply voltage has to be guaranteed by proper application design. to reduce the emi noise filtering, the device embeds a proprietary frequency jittering technique. STCH01 allows to achieve zero power consumption consumption in no load operation thanks to the following features: ? low operating v dd voltage ? low operating quiescent current ? intelligent burst mode operation, with wake-up from secondary side (optoless version) ? built-in high voltage active start-up circuit, based on depletion mosfet in addition to these functions that optimize power handling under different operating conditions, the device offers protection features with autorestart functionality that considerably increase end product's safety and reliability: ? thermal shutdown with hysteresis ? feedback disconnection feature ? second level ocp against transformer saturation or secondary diode short-circuit
docid026783 rev 2 5/58 STCH01 device description 58 the device allows a system level trimming that improves application performance and manufacturing process. the parameters that can be adjusted by on line digital trimming are: ? output voltage accuracy setting ? output current accuracy setting ? voltage feed-forward accuracy setting ? frequency jitter amplitude an ovp pin is also provided, with sensing from the auxiliary winding and latched functionality. furthermore, the device is equipped with a pin prot, for a generic user defined protection circuit (like ovp or otp): this can be the latched type or autorestart, according to the selected bit option. an embedded soft-start procedure and leading edge blanking on the current sense input for greater noise immunity complete the equipment of this device.
block diagram STCH01 6/58 docid026783 rev 2 2 block diagram figure 1. block diagram
docid026783 rev 2 7/58 STCH01 pin functions and typical power 58 3 pin functions and typical power table 2. pin functions name function vin input bus voltage (from the rectified mains) connected to the drain of the internal high-side mosfet. pins connected to the internal metal frame to facilitate heat dissipation. drain drain connection of the internal low-side power mosfet. the internal high voltage start-up generator sinks current from these pins as well. pins connected to the internal metal frame to facilitate heat dissipation. cres a capacitor connected between this pin and the drain pin sets the resonant frequency occurring after the low-side mosfet turn-off (during transformer demagnetization). cdrv a capacitor connected between this pin and the drain pin allows high-side mosfet self-driving: this mosfet is turned-on when drain voltage is higher than vin voltage and is turned-off when drain voltage is lower than vin voltage. src source connection of the internal low-side mosfet and input to the pwm and 2 nd -ocp comparators. the current flowing in the low-side mosfet is sensed through a resistor connected between the src pin and gnd. the resulting voltage is sent to internal comparators to determine the mosfet's turn- off. gnd circuit ground reference and current return for both the signal part of the ic and the gate drive. all ground connections of the bias components should be tied to a trace going to this pin and kept separated from any pulsed current return (sense resistor between the src pin and gnd). vdd supply voltage of the device. an electrolytic capacitor, connected between this pin and ground, is initially charged by the internal high voltage start-up generator; when the device is running the same generator will keep it charged in case the voltage suppl ied by the auxiliary winding is not sufficient (for example this may happen during cc regulation). this feature is disabled in case of protection tripping. sometimes a small bypass capacitor (0.1 f typ.) to gnd might be useful to get a clean bias voltage for the signal part of the ic. iref cc regulation loop reference voltage. an external capacitor connected between this pin and gnd is charged by an internal circuit to an appropriate voltage level that is used as the reference for the mosfet's peak drain current during cc regulation. the voltage is automatically adjusted to keep constant the average output current.
pin functions and typical power STCH01 8/58 docid026783 rev 2 zcd the following functions are performed by this pin: ? transformer demagnetization sensing for quasi-resonant operation. a negative going edge falling below the v zcdt threshold triggers the mosfet turn-on, provided the internal circuit has been previously armed by a positive going edge exceeding the v zcda threshold. ? input voltage feed-forward compensation. by connecting the zcd pin to the auxiliary winding through a resistor, the current sourced by the pin during the mosfet on-time is monitored to get an image of the input voltage to the converter. this information is used by the internal circuitry to achieve a cc regulation independent of the mains voltage. ? output voltage sense through a resistive divider connected to the auxiliary winding. the voltage on the low-side resistor of the divider (connected to this pin) is sampled and held right at the end of transformer's demagnetization to get an accurate image of the output voltage to be fed to the inverting input of the internal transconductance type error amplifier. ? sensing of wake-up signal coming from the secondary side during the burst mode, through the transformer auxiliary winding (optoless version). ? feedback disconnection. if the current sourced by the pin during the low-side mosfet turn-on does not exceed 50 a, either a floating pin or an abnormally low input voltage is assumed, the device is stopped and restarted after v dd voltage has dropped below v dd_restart . ? please note that the maximum i zcd sunk/sourced current has to not exceed the values indicated in the amr section table 4: absolute maximum ratings in all the vin range conditions (88 - 265 vac). no capacitor is allowed between this pin and the transformer auxiliary winding. comp ? optoless version: output of the internal transconductance error amplifier. the compensation network will be placed between this pin and gnd to achieve stability and good dynamic performance of the voltage control loop. ? opto version: control input for duty cycle control. an internal current generator provides a bias current for voltage loop regulation (implemented through secondary side sensing and optocoupler), while the internal transconductance error amplifier is disabled and internally disconnected from the pin. a voltage below the threshold v compbm activates the burst mode operation. ovp/scl a multiplexed pin for the overvoltage protection input during the normal operation and online trimming clock input. ? output voltage sense through a resistive divider connected to the auxiliary winding for overvoltage protection purpose: the voltage sensed on this pin is compared with an internal reference v ovp at the time instant when the transformer is demagnetized (and the auxiliary winding voltage is a representative value of the output voltage through the turn ratio); if the internal threshold v ovp is surpassed, then an overvoltage condition is assumed and the circuit enters a latched protection mode. after protection tripping, a mains recycle is necessary for a new restart attempt. ? in case ovp function is not used, the pin has to be connected to gnd through a resistor (5 k to 30 k ). ? clock (scl) logic input for i 2 c serial communication protocol. this pin will be externally pull-up to 3.6 v max. a small internal pull-up is present to prevent false signal detection (the pin is floating during normal operation). prot/sda a multiplexed pin for a generic protection input during normal operation and online trimming data input. ? generic protection input pin (active low): when the voltage on this pin is lower than the v prot threshold, the protection detection circuit stops device operation (latch type or autorestart mode according to the selected option). if this pin is not used, keep it open (not connected). ? data (sda) logic input/output for i 2 c serial communication protocol. this pin will be externally pull- up to 3.6 v max. a small internal pull-up is present to prevent false signal detection (the pin is floating during normal operation). table 2. pin functions (continued) name function
docid026783 rev 2 9/58 STCH01 pin functions and typical power 58 table 3. typical power part number 230 v ac 85-265 v ac adapter (1) 1. typical continuous power in non-ventilat ed enclosed adapter measured at 50 c ambient open frame (2) 2. maximum continuous power in an open frame design at 50c ambient with adequate heat sinking adapter (1) open frame (2) STCH01 12.5w 18w 10w 12.5w
maximum ratings STCH01 10/58 docid026783 rev 2 4 maximum ratings stressing the device above the rating listed in table 4: absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions may affect device reliability. table 4. absolute maximum ratings symbol parameter value unit v ds_ls_mos low-side mosfet drain-to-source voltage 650 v v ds_hs_mos high-side mosfet drain-to-source voltage 500 v e av-ls-mos single pulse avalanche energy, starting t j = 25 c, i d = i as = 0.7 a (single pulse avalanche current) (1) 1. pulse width limited by t j = 150 c. 20 mj e av-hs-mos single pulse avalanche energy, starting t j = 25 c, i d = i as = 0.7 a (single pulse avalanche current) (1) 20 mj i drain (ls-mos) low-side mosfet drain current (pulsed) 1.5 a i drain (hs-mos) high-side mosfet drain current (pulsed) 1.5 a v d-rrm diode (d) for high-side mosfet drive repetitive peak reverse voltage 300 v i fd diode (d) for high-side mosfet drive forward current (pulsed, 200 ns) 0.2 a i fzd1,2 internal diodes (zd1, zd2) forward current (pulsed, 200 ns) 0.2 a v dd device supply voltage (i dd < 25 ma) -0.3 to self-limited v v zcd zcd pin voltage (-3 ma i zcd +3 ma) -0.3 to self-limited v v ovp ovp pin voltage (-3 ma i zcd +3 ma) -0.3 to self-limited v v prot protection pin voltage -0.3 to 3 v - analog/digital pin voltages -0.3 to 3.6 v table 5. thermal data symbol parameter value unit r th-amb thermal resistance junction ambient (1) 1. mounted on a standard single side fr4 board with 50 mm 2 of cu (35 m thick) under drain and vin pins. 120 c/w p tot max. power dissipation at t amb = 50 c 0.8 w t j junction temperature range -40 to 150 (2) 2. max t j = 150 c refers to the embedded mosfet. c t stg storage temperature -55 to 150 c
docid026783 rev 2 11/58 STCH01 maximum ratings 58 figure 2. device pinout (top view) 1. the copper area for heat dissipation has to be designed under the highlighted pins, connected respectively to drain and vin signals. vin comp zcd iref n.c. src gnd vdd drain drain ovp/scl n.c. n.c. prot/sda cre cdrv STCH01 am03702
electrical characteristics STCH01 12/58 docid026783 rev 2 5 electrical characteristics table 6. electrical characteristics (t j = -25 c to 125 c, v dd = 8 v; unless otherwise specified) symbol parameter test condition min. typ. max. unit low-side mosfet v (br)dss drain-source breakdown voltage i drain < 100 a; t j = 25 c 650 v i off off state drain leakage current v ds = 650 v; t j = 125 c, v dd = 8 v, v comp < v compbm , v zcd connected to gnd 4a r ds(on) static drain-source on- resistance i d = 1 a; t j = 25 c 4 i d = 1 a; t j = 125 c 8.8 c osseq. equivalent output capacitance v ds = 0 to 480 v; t j = 25 c 30 pf high-side mosfet v (br)dss drain-source breakdown voltage i drain < 100 a; t j = 25 c 500 v i off off state drain leakage current v ds = 500 v; t j = 125 c 1 a r ds(on) static drain-source on- resistance v cdrv - v cres = 10 v; i d = 1 a; t j = 25 c 8 v cdrv - v cres = 10 v; i d = 1 a; t j = 125 c 17.6 c osseq. equivalent output capacitance v ds = 0 to 480 v; t j = 25 c 25 pf internal diode (d) for high-side mosfet drive v r reverse voltage i r < 1 a 300 v v f forward drop i f = 20 ma; t j = 25 c 1 v internal zener diodes (zd1, zd2) for high-side mosfet drive v zd1,2 zd1, 2 zener voltage i r = 5 ma; t j = 25 c 10 15 20 v v fzd1,2 zener diode forward drop i f = 2 ma; t j = 25 c 1.7 1.9 v r d1,2 dynamic resistance i f = 2 to 10 ma; t j = 25 c 300 supply section v ds_start drain-source start voltage 55 62 67 v
docid026783 rev 2 13/58 STCH01 electrical characteristics 58 i dd_ch start-up charging current v drain > v ds_start ; v dd = 4 v -3.5 -5.5 -8 ma v drain > v ds_start ; v dd < 0.6 v (v dd shorted or after protection tripping) -0.7 -1.1 -1.72 ma v dd operating voltage range after turn-on 5.75 23.5 v v dd_clamp v dd clamp voltage i dd = 5 ma 23.5 v v dd_on v dd turn-on threshold v drain = 120 v 10 11 (1) 12 v v dd_off v dd shutdown threshold 4.75 5.25 (1) 5.75 v v dd_restart v dd (falling) restart voltage normal operation 5 5.5 (1) 6v after autorestart or latch protection 4.5 5 (1) 5.5 v i dd_st-up before start-up current v drain > v ds_start ;250a i ddo quiescent current (not switching between bursts) v comp = v compl (no opto) v dd = v dd_on - 0.2 v 50 a v comp = v compl , (with opto) 350 a i dd operating supply current v ds = 120 v; f sw = 100 khz 1.3 ma i dd_fault operating supply current with protection tripping prot open 350 a prot shorted 550 a controller section zero current detection i zcd_bias input bias current v zcd = 0.1 to 3 v 1 a v zcd_h upper clamp voltage i zcd = 1 ma 3.3 v v zcd_l lower clamp voltage i zcd = -1 ma -60 mv v zcd_a_th arming voltage threshold positive going edge 110 mv v zcd_t_th trigger voltage threshold negative going edge 60 mv i zcd_on minimum source current during mosfet on-time -25 -50 -75 a t blank blanking time after turn-on v comp > 1.3 v 6 s v comp < 0.9 v 30 s t d_zcd fixed turn-on delay after zcd triggering 450 ns wake-up pulse detection (optoless version) v zcdwupth wake-up threshold on zcd pin (for burst-mode exiting) positive going edge 0.6 0.7 0.8 v t wup_min min wake-up pulse width above wake-up threshold 1.2 s table 6. electrical characteristics (t j = -25 c to 125 c, v dd = 8 v; unless otherwise specified) (continued) symbol parameter test condition min. typ. max. unit
electrical characteristics STCH01 14/58 docid026783 rev 2 t wup_mask wake-up masking time after burst-mode entering 46 50 54 s transconductance error amplifier v ref voltage reference (1) v dd within supply range 2.45 2.5 2.55 v gm transconductance i comp = 10 a v comp = 1.65 v 1 ms gv voltage gain open loop 70 db gb gain-bandwidth product 0.5 mhz i comp source current v zcd = 2.3 v, v comp = 1.65 v 70 100 a opto bit option 70 100 130 a sink current v zcd = 2.7 v, v comp = 1.65 v 550 750 a v comph upper comp voltage v zcd = 2.3 v 2.7 v v compl lower comp voltage v zcd = 2.7 v 0.7 v v compbm burst mode threshold voltage falling 0.95 v hys burst mode hysteresis voltage rising 50 mv current reference v irefx maximum value (1) v comp = v compl 1.5 1.6 1.7 v g i current loop gain (2) v comp = v comph 0.5 v cref current reference voltage 0.4 v g i * v cref 190 200 210 mv current sense v csx max. clamp value (1) dvcs/dt = 200 mv/s 0.7 0.75 0.8 v v csdis hiccup mode ocp level 0.92 1 1.08 v t d propagation delay 250 ns t leb leading edge blanking 250 ns t on_min minimum on-time 500 ns input voltage feed-forward r ff equivalent ff resistor i zcd = -1 ma 54 60 66 frequency jittering f m modulation frequency 10 11 12 khz duty modulation duty cycle 50 % ipk peak current change (default bit option) 5 % starter t starter starter period zcd not armed 180 s table 6. electrical characteristics (t j = -25 c to 125 c, v dd = 8 v; unless otherwise specified) (continued) symbol parameter test condition min. typ. max. unit
docid026783 rev 2 15/58 STCH01 electrical characteristics 58 ovp function v ovp overvoltage threshold (1) v dd within supply range 1.204 1.254 1.304 v v ovp_h upper clamp voltage i zcd = 1 ma 3.3 v v ovp_l lower clamp voltage i zcd = -1 ma -60 mv protection pin v prot_sd shutdown threshold 1.204 1.254 1.304 v i s source current v prot = 1.24 v -165 -200 -225 a i s_fault source current v prot = 0 v, v dd rising from v dd _ restart to 11 v autorestart option -125 -150 -175 a v prot = 0 v, v dd rising from v dd_restart to 11 v latch option -20 a v prot-clp clamp voltage pin open 3 v c max max external capacitance 13 pf trimming functions v scl_low scl input low level 0.8 v v scl_hi (2) scl input high level 2 3.45 v c scl scl input capacitance 5 pf f scl scl frequency 100 khz v sda_low sda input low level 0.8 v v sda_hi (2) sda input high level 2 3.45 v c sda sda input capacitance 5 pf v ddzap prom zapping voltage 17 20 v i zap prom zapping current v dd = 19 v 50 90 ma t zap prom zapping time v dd = 19 v 34 45 ms v ref trimming range (5 bits) referred to 0% trimming -9 9 % v ref trimming step 0.6 % g i * v cref trimming range (4 bits) referred to 0% trimming -10.5 10.5 % g i * v cref trimming step 1.5 % r ff trimming range (3 bits) referred to 0% trimming -17.5 17.5 % r ff trimming step 2.5 % ipk frequency jitter amplitude levels:% of peak current change no jitter 0 % default value. for the other values, refer to table 19 . 5% 1. all voltages in tracking. 2. sda and scl inputs are connected to an internal bus at 3.3 v even if they are protected to v dd as amr. table 6. electrical characteristics (t j = -25 c to 125 c, v dd = 8 v; unless otherwise specified) (continued) symbol parameter test condition min. typ. max. unit
typical application - optoless version STCH01 16/58 docid026783 rev 2 6 typical application - optoless version figure 3. typical +5 v -8 w charger application electrical diagram 1 2 j1 con2 1 2 j2 con2 + - ~ ~ d1 df06s c1 10uf-400v out 1 gnd 2 nc3 3 vsns 4 nc5 5 vdd 6 u2 stwk01 c4 47pf-500v c11 4.7nf c3 220pf-500v r5 60.4k c2 4.7uf-400v r6 68k r8 47k r3 12k c10 150nf prot-sda l2 330uh c7 res +5v l1 2x10mh c9 1nf ovp-scl c8 100nf r9 2r2 d3 bav103 c12 10uf-50v +5v d2 sbr10u45 c5 270uf-6.3v r1 fuse-4r7 r2 0.75r 1 2 3 4 j3 con4_0 prot/sda ovp/scl vdd vdd c6 560uf-6.3v 4 8 6 5 2 1 7 9 t1 e20-1.5mh vin 1 nc2 2 src 3 vdd 4 gnd 5 iref 6 zcd 7 prot/sda 10 nc11 11 drain 12 drain 13 nc14 14 cdrv 15 cres 16 comp 8 ovp/scl 9 u1 STCH01 r7 res r10 360k r11 33k c13 470pf-y 1 r4 14.3k am03703
docid026783 rev 2 17/58 STCH01 typical application - opto version 58 7 typical application - opto version figure 4. typical +5 v -8 w charger application electrical diagram 1 2 j1 co n2 1 2 j2 con2 r14 68k r15 21.5k + - ~ ~ d1 df06s c1 10uf-400v c4 47pf-500v c11 4.7nf c3 220pf-500v r5 60.4k c2 4.7uf-400v u4 ts431 prot-sda l2 330uh c7 res l1 2x10mh c9 470pf ovp-scl c8 100nf r9 2r2 c10 100nf d3 bav103 r13 15k c14 10n r3 22k c12 10uf-50v +5v u3a sfh617a-2 d2 sbr10u45 c5 270uf-6.3v u3b sfh617a-2 r6 res r1 fuse-4r7 r12 470 +5v r2 0.75r 1 2 3 4 j3 con4_0 prot/sda ovp/scl vdd vdd c6 560uf-6.3v 4 8 6 5 2 1 7 9 t1 e20-1.5mh vin 1 nc2 2 src 3 vdd 4 gnd 5 iref 6 zcd 7 prot/sda 10 nc11 11 drain 12 drain 13 nc14 14 cdrv 15 cres 16 comp 8 ovp/scl 9 u1 STCH01 r10 360k r11 33k c13 470pf-y 1 r4 14.3k am03704
operation description STCH01 18/58 docid026783 rev 2 8 operation description the STCH01device is a high-performance switching regulator, specific for off-line qr flyback topology; it combines a low-voltage pwm controller with two avalanche rugged power mosfets in the same package: the low-side one is the main switch of the topology, the high-side one is used for controlling the resonant frequencies. in the optoless version, the controller includes the current mode pwm logic and the zcd circuit for qr operation, and regulates the output voltage and current, basing on primary-sensing feedback. the auxiliary winding voltage is sampled by a sample and hold circuit just at the end of transformer demagnetization, when its voltage is proportional to the output voltage through the transformer turn ratio, triggered by the demagnetization sensing circuit. the sensed voltage is then sent to the error amplifier and its output to the constant voltage pwm comparator. the demagnetization circuit also allows obtaining a reference voltage (proportional to the output current) for the constant current pwm comparator. in the opto version, the internal error amplifier is disabled and a current generator provides to the comp pin the required feedback current, allowing to regulate the output voltage (sensed at the secondary side) through the optocoupler connected to the comp pin. the device provides protection features with autorestart functionality that increases the end product safety and reliability, like the feedback disconnection protection, the second level ocp circuit (suitable for detection of transformer saturation or output diode short-circuit) and the thermal shutdown with hysteresis. a dedicated protection pin (prot) is also available for a generic user defined protection (like otp or ovp), that can be autorestart or latched, according to the selected device version. other features, like an embedded soft-start, frequency jitter for emi reduction and leading edge blanking on the current sense input, complete the device equipment, giving the user flexibility and ease of use in designing an end product very robust and performing, with high-efficiency and extremely low no load consumption as well and, above all, with a very low component count. the pwm logic works in the qr mode at the nominal load, in the valley-skipping mode at a lighter load and in the burst mode with a very low load or no load. in the qr mode the controller turns on the low-side power mosfet at the end of the transformer demagnetization, by detecting the resulting negative going edge of the voltage across the auxiliary winding of the transformer. the mosfet turn-off is instead decided by the pwm comparator when the drain current reaches the peak value needed for the output voltage or the output current regulation; therefore the operating switching frequency will be different for different line and load conditions. at lower load levels, the valley-skipping mode is activated. in fact, depending on the comp pin voltage, a blanking time from the turn-on instant (increasing with decreasing comp voltage) is internally set, limiting the maximum operating frequency. as a consequence, the mosfet turn-on will not any more occur on the first valley but on the second one, the third one and so on. in this way a ?frequency clamp? effect is achieved (see figure 5 ).
docid026783 rev 2 19/58 STCH01 operation description 58 figure 5. frequency mode operation versus load while reducing the load, the comp pin voltage progressively reduces: at no load or a very light load, it goes below the threshold v compbm and consequently the controller stops operation and reduces its consumption. with the opto version, the operation restarts as soon as the comp pin, due to feedback reaction at the operation stop, increases above the v compbm level plus the burst mode hysteresis (hys). in case of the optoless version, instead, once stopped the operation, the controller remains in a very low consumption state waiting for a wake-up signal pulse (on zcd pin). a dedicated ic at the secondary side (stwk01 companion of the primary controller optoless version) detects the primary side operation stop and starts monitoring the output voltage: when this decreases (due to the residual output consumption) below a user defined voltage threshold, the stwk01 ic releases a wake-up pulse via the transformer windings, that is sensed by the zcd pin through the resistive divider connected to the auxiliary transformer winding; consequently the STCH01controller resumes operation (see section 8.9: burst mode operation (optoless version) on page 30 . 8.1 low-side power section and gate driver the low-side power section guarantees safe avalanche operation within the specified energy rating as well as high dv/dt capability. the power mosfet gate driver is designed to supply a controlled gate current during both turn-on and turn-off in order to minimize the common mode emi. under uvlo conditions, an internal pull-down circuit holds the gate low in order to ensure that the power mosfet cannot be turned on accidentally. the driver is also provided with a voltage clamp to limit the gate charge to the mosfet in case of higher v dd supply. %xuvwprgh 9dooh\vnlsslqj prgh 45prgh ) pd[ ) 6: 3rxw ,qfuhdvlqj 9 ,1 $0
operation description STCH01 20/58 docid026783 rev 2 8.2 high-side power section and resonant frequency control the device integrates also a high-side power section to control resonant frequencies. the high-side mosfet connects and disconnects a capacitor cr (placed between cres and drain pins) in parallel to the primary winding of the power transformer. in this way the converter operates at two different resonant frequencies: a high resonant frequency when cr is disconnected and a lower resonant frequency when cr is connected to the transformer primary inductance. the energy stored in the circuit during the two portions of resonant cycles in principle may provide zvs (?zero voltage switching?) operation for both low and high-side power mosfets, thus increasing the overall converter efficiency. the mosfet is automatically driven on and off depending on the external circuit operation; only a capacitor (47 - 100 pf) is needed, connected between the cdrv and drain pins. in particular the high-side mosfet is on when the drain voltage across the low-side mosfet is higher than the input voltage and is off when the drain voltage is lower than vin. 8.3 high voltage startup generator based on a depletion mosfet embedded into the low-side mosfet structure, the hv current generator is supplied through the drain pin and is enabled only if the input bulk capacitor voltage is higher than the v ds_start threshold. when the hv current generator is on, the i dd_ch current is delivered to the capacitor on the v dd pin. as the voltage across the v dd capacitor reaches the start-up threshold v dd_on , the uvlo signal is asserted high and enables the low-side mosfet switching, while the hv current generator is turned off. the ic is powered by the energy stored in the v dd capacitor until the self-supply circuit (from an auxiliary winding of the transformer) develops a voltage high enough to sustain the operation. the chip is able to power itself directly from the rectified mains through the hv start-up circuit: when the voltage on the v dd pin falls below v dd_restart, during each mosfet's off- time, the hv current generator is turned on and charges the supply capacitor until it reaches the v dd_on threshold again. in this way, the self-supply circuit develops a voltage high enough to sustain the operation of the device. this feature is useful especially during cc regulation, when the flyback voltage generated by the auxiliary winding alone may be not enough to keep v dd above v dd_restart . after an autorestart type protection tripping, the v dd_restart value is reduced (below v dd_off ) and the hv generator provides only about 20% of i dd_ch full value, allowing for a lower repetition rate of restart attempts (reduced input power consumption and depletion mosfet stress). when at no load or a very light load the controller stops operating and remains waiting for the wake-up signal, the vdd is not controlled and the hv start-up generator is not restarted in case the v dd_restart is reached. therefore, during the burst mode operation the vdd voltage has to be always higher than v dd_off by a proper design of the transformer auxiliary winding turns and of the capacitor value on the v dd pin. figure 6 shows the time diagram during the various operating conditions, from power-on to power-off, with the typical restart during cc regulation, when the transformer auxiliary winding is not enough to sustain the device supply voltage. at converter power-down the system will lose regulation as soon as the input voltage falls below v ds_start . this prevents
docid026783 rev 2 21/58 STCH01 operation description 58 converter's restart attempts and ensures monotonic output voltage decay at system power- down. in order to avoid overheating of the hv current generator in case of a short-circuit on v dd , the full current i dd_ch is delivered only if the v dd voltage is detected higher than a v be threshold, otherwise it is reduced to about 20% of i dd_ch full value. figure 6. timing diagram from power-on to power-off 9 '' w w w w 9 '6b67$57 w w 3rzhu rq 3rzhu rii 1rupdorshudwlrq &9prgh &&prgh 1rupdorshudwlrq w w w w 9lq , ''b&+ w w 3rzhu rq 3rzhu rii 1rupdorshudwlrq &9prgh &&prgh 1rupdorshudwlrq 9 ''buhvwduw 9 ''brq '5$,1 $0
operation description STCH01 22/58 docid026783 rev 2 8.4 zero current detection circuit the quasi-resonant operation is accomplished through the zero current detection (zcd) circuit, which allows the turn-on of the power section at the end of the transformer demagnetization. the input signal for the zcd pin is obtained from the transformer auxiliary winding, the same used to get the v dd supply voltage of the controller ( figure 7 ). figure 7. zcd circuit and turn-on logic the voltage on the zcd pin is both top and bottom limited by a double clamp: the upper clamp v zcd_h (positive) and the lower clamp v zcd_l (negative). the interface between the zcd pin and the auxiliary winding is a resistor divider. the resistance ratio as well as the individual resistance values have to be properly chosen (see section 8.5: constant voltage regulation (optoless version) on page 24 and section 8.6: constant voltage regulation (opto version) on page 25 and section 8.8: voltage feed-forward block on page 28 ). when the triggering circuit senses a negative going edge of the signal applied to the zcd pin going below the v zcd_t_th threshold, the internal low-side mosfet is turned on, after a fixed delay that helps to achieve the minimum drain-source voltage, resonating after the demagnetization. however, to enable the mosfet turn-on, the triggering circuit has to be previously armed by a positive going edge of the zcd pin voltage exceeding the v zcd_a_th threshold. a starter block allows to turn on the mosfet during the converter power-up, when no or a too small signal is available on the zcd pin. after the first few cycles initiated by the starter, as the voltage developed across the auxiliary winding becomes large enough to arm the zcd circuit, the mosfet's turn-on will start to be locked to transformer demagnetization, hence setting up qr operation. the starter is activated also when the ic is in cc regulation and the output voltage is not high enough to allow the zcd triggering. after the mosfet turn-on, a blanking time is inserted, whose value depends on the comp pin voltage: it is t blank = 30 s for v comp = 0.9 v, and decreases almost linearly down to t blank = 6 s for v comp 1.3 v. this blanking time has two aims; the first is to prevent erroneous triggering due to the noise generated after the demagnetization of the transformer leakage inductance; the second is to avoid the operating frequency may increase above certain limits that would impair system efficiency, especially in medium and light load operation and high input voltage. 7kuhuvkrogv =&' &/$0 3 %/$1.,1* 7,0( 785121 /2*,& 6 5 4 /(% $x[ 5 )% 5 =&' 7rgulyhu )urp&&&9eorf n )urp2&3 67$57(5 =&' $upwuljjhu $0
docid026783 rev 2 23/58 STCH01 operation description 58 as a consequence of the blanking time, the mosfet turn-on may occur not on the first valley but on the second one, the third one and so on, depending on the operating condition, leading to a valley-skipping mechanism that progressively reduces the operating frequency and improves system efficiency. figure 8 shows the valley-skipping mechanism: if the demagnetization completes - hence a negative going edge appears on the zcd pin - after a time exceeding time t blank from the previous turn-off, the mosfet will be turned on again, (with a fixed delay to ensure minimum voltage at turn-on). if, instead, the negative going edge appears before t blank has elapsed, it will be ignored and only the first negative going edge after t blank will turn- on the mosfet. in this way one or more drain ringing cycles will be skipped and the switching frequency will be prevented from exceeding 1 / t blank . figure 8. valley-skipping at progressively reduced load when the system operates in the valley-skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the mosfet is allowed to change with discrete steps of one ringing cycle, while the off-time needed for cycle-by-cycle energy balance could fall in between. thus one or more longer switching cycles will be compensated by one or more shorter cycles and vice versa. this mechanism is natural and there is no appreciable effect on the converter's performances and on its output voltage. 45rshudwlrq 9dooh\vnlsslqj rshudwlrq vw ydooh\ 9 '6 9,1 7 %/$1. 7 %/$1. qg ydooh\ ug ydooh\ 9,1 9,1 $0
operation description STCH01 24/58 docid026783 rev 2 8.5 constant voltage regulation (optoless version) the ic is internally configured to work in the primary side regulation mode: the output voltage is sensed through a voltage partition of the auxiliary winding, just before the auxiliary rectifier diode. figure 9 shows the internal schematic of the constant voltage regulation circuitry and the external connections. due to the parasitic wires resistance, the auxiliary voltage is representative of the output just when the secondary current becomes zero. for this purpose, the signal on the zcd pin is sampled and held at the end of transformer's demagnetization to get an accurate image of the output voltage and it is compared to the error amplifier internal reference. figure 9. constant voltage regulation: internal schematic (optoless version) during the mosfet's off-time the leakage inductance resonates with the total capacitance across the mosfet drain-source, and a damped oscillation is superimposed on the reflected voltage. the s/h logic is able to discriminate such oscillations from the real transformer's demagnetization. when the zcd logic detects the transformer's demagnetization, the sampling process stops, the information is frozen and compared with the error amplifier internal reference. the internal error amplifier is a transconductance type and delivers an output current proportional to the input voltage unbalance: its output generates the control voltage that is compared to the voltage across the sense resistor, thus modulating the cycle-by-cycle peak drain current. the comp pin is used for the frequency compensation: usually, an rc network, which stabilizes the overall voltage control loop, is connected between this pin and ground. further capacitor between the comp and gnd may be used to set a high frequency pole in the circuit compensation. the output voltage v out can be set by fixing r zcd and choosing the resistor r fb according to equation 1 .
docid026783 rev 2 25/58 STCH01 operation description 58 equation 1 where n sec and n aux are the secondary and auxiliary turn number respectively. the r zcd value can be defined depending on the application parameters (see section 8.8: voltage feed-forward block on page 28 ). 8.6 constant voltage regulation (opto version) the ic is internally configured to work in secondary side regulation (the internal transconductance error amplifier is disabled and disconnected from the comp pin); the output voltage is sensed through a voltage partition across the output capacitor, and the feedback signal obtained at the output of the error amplifier (also located at secondary side), is sent to the primary side through an optocoupler connected to the comp pin. figure 10 shows the internal schematic of the constant voltage regulation circuitry and the external connections for the opto version. figure 10. constant voltage regulation: internal schematic (opto version) an internal current generator connected on the comp pin provides the required feedback current to the optocoupler transistor, allowing to regulate the output voltage. a resistor and a capacitor between the comp and gnd may be used to set a high frequency pole in the circuit compensation. a further resistor and capacitor series connected and placed between the comp and gnd may be used for adapting the required loop compensation gain and obtaining the proper system dynamic behavior. the demagnetization logic block, not necessary for voltage regulation, is still necessary for constant current regulation; therefore the external resistive divider (r zcd - r fb ) is still necessary and has to be properly set: for r zcd selection refer to section 8.8: voltage feed- forward block , while for r fb selection equation 1 is still valid. = & ' 5 ( ) 2 8 7 6 ( & $ 8 ; 5 ( ) ) % 5 9 9 1 1 9 5 ? ? ? =
operation description STCH01 26/58 docid026783 rev 2 8.7 constant current regulation figure 11 presents the basic principle used for controlling the average output current of a flyback converter. the auxiliary winding voltage is used by the demagnetization block to generate the control signal for the switch q1. the flip-flop output is high as long as the transformer delivers the current on the secondary side (i.e. during transformer demagnetization). during the time period where the switch q1 is open, the reference current i ref flows through the external capacitor c ref on the iref pin; during the on time of the switch q1, the resistor r absorbs a current v c /r, where v c is the voltage developed across the capacitor c ref . this current balance is shown in figure 12 . figure 11. constant current regulation: internal schematic figure 12. constant current operation: switching cycle waveforms w w w w , 3 , v 4*dwh , & 7 5 9 , & 5() 5() , $0
docid026783 rev 2 27/58 STCH01 operation description 58 the capacitor value has to be chosen so that its voltage v c can be considered constant. since it is charged and discharged by currents in the range of some ten a at the switching frequency rate, a capacitance value in the range 4.7 - 10 nf is suitable for switching frequencies in the ten khz. the average output current can be expressed as: equation 2 where i s is the secondary peak current, t onsec is the conduction time of the secondary side and t is the switching period. taking into account the transformer ratio n = n prim / n sec between the primary and secondary side, i s can also be expressed as a function of the primary peak current i p : equation 3 as in steady state the average current i c through the external capacitor c ref on the iref pin has to be zero: equation 4 the following expression is found for v c : equation 5 where v cref = r ? i ref . as v c is fed to the cc comparator, the primary peak current can be expressed as: equation 6 combining equation 2 , equation 3 , equation 5 and equation 6 , the expression of the output current is found: equation 7 ? ? ? ? ? ? ? = 7 7 , , 2 1 6 ( & 6 2 8 7 3 6 , q , ? = () 2 1 6 ( & & 5 ( ) 2 1 6 ( & 5 ( ) 7 5 9 , 7 7 , ? ? ? ? ? ? ? ? ? = ? ? ( ( ) ? = ? = 6 1 6 & 5 ( ) , 2 8 7 5 9 * q , ? ? =
operation description STCH01 28/58 docid026783 rev 2 this formula shows that the average output current does not depend anymore on the input or the output voltage, neither on transformer inductance values. the external parameters defining the output current are the transformer ratio n and the sense resistor r sns . the current loop gain g i and current reference voltage v cref are internally defined. g i can be trimmed in order to provide an accurate cc set point. the soft-start feature is automatically implemented by the constant current regulation circuit, as the primary peak current is limited by the voltage on the c ref capacitor. during the startup, as the output voltage is zero, the ic will start in the cc mode with no high peak current operations. in this way the voltage on the output capacitor will increase slowly and the soft-start feature will be ensured. actually the c ref value is not relevant to define the soft-start time, as its duration depends on other circuit parameters, like the transformer ratio, sense resistor, output capacitors and load. the user will define the best appropriate value by experiments. 8.8 voltage feed-forward block the current control circuit uses the voltage v c to define the output current, according to equation 7 . actually, the cc comparator will be affected by an internal propagation delay t d , which will switch off the mosfet at a peak current higher than the foreseen value. this current overshoot is calculated through equation 8 : equation 8 it introduces an error on the calculated cc set point, depending on the input voltage, according to equation 9 : equation 9 the device implements a line feed-forward function, which solves the issue by introducing an input voltage dependent offset on the current sense signal, in order to adjust the cycle- by-cycle current limitation. the internal schematic is shown in figure 13 . 3 ' , 1 3 / 7 9 a , ? = 3 ' , 1 & & 5 ( ) 2 8 7 ( 5 5 / 7 9 9 9 q , ? ? ? ? =
docid026783 rev 2 29/58 STCH01 operation description 58 figure 13. voltage feed-forward circuit during the mosfet on-time the current sourced from the zcd pin is mirrored in order to provide a feed-forward current i ff proportional to the input voltage according to equation 10 : equation 10 where m is the primary-to-auxiliary turns ratio (n prim / n aux ). according to the schematic in figure 13 , the voltage on the non inverting pin of cc comparator will be: equation 11 the offset introduced by the feed-forward compensation will be: equation 12 as r ff >> r sns , the previous one can be simplified as: equation 13 this offset is proportional to v in and is used to compensate the current overshoot, according to: equation 14 = & ' , 1 ) ) 5 p 9 , ? = () ) ) 6 1 6 ) ) ' 6 1 6 "! , 5 5 , 5 9 ? + + ? = + () 6 1 6 ) ) = & ' , 1 2 ) ) 6 ( 7 5 5 5 p 9 9 + ? ? = = ) ) ) ) ( ? ? = = & ' ) ) , 1 6 1 6 3 g , 1 5 p 5 9 5 / 7 9 ? ? = ? ?
operation description STCH01 30/58 docid026783 rev 2 finally, the r zcd resistor can be calculated as follows: equation 15 in this case the peak drain current does not depend on input voltage anymore. one more consideration concerns the r zcd value: during the mosfet's on-time, the current sourced by the zcd pin, i zcd , is compared with an internal reference current i zcdon . if i zcd < i zcdon , the brownout function is activated and the ic is shut down. this feature is especially important when the auxiliary winding is accidentally disconnected or the zcd pin is short-circuited to gnd (i zcd = 0 that means a feedback loop disconnection occurs) and considerably increases the end product's safety and reliability. 8.9 burst mode operation (optoless version) with decreasing load levels, when the voltage at the comp pin falls below the threshold v compbm , the ic is disabled with the mosfet kept in off state and its consumption reduced at a very low value to minimize v dd capacitor discharge: in this state only few ic blocks are kept alive, dropping the device consumption to few tens a. the device will resume operation only after a wake-up signal, coming from the secondary side via the transformer, is sensed on the zcd pin. for this purpose, as shown in figure 14 , stwk01at the secondary side senses the output voltage and when it falls below a threshold set by the resistive divider (r1, r2), a switch across the output diode is turned on for a fixed time (about 1 s), transferring a pulse train from the secondary winding to the auxiliary winding and hence to the zcd pin. the stwk01 logic enables the check on the output voltage only after it has detected the switching operation stop: this is to avoid wake-up pulses during the switching activity that would cause a short-circuit across the secondary winding of the flyback transformer. figure 14. secondary side wake-up circuit 6 1 6 g ) ) 3 3 5 , 0 $ 8 ; = & ' 5 7 5 / 1 1 5 ? ? ? =
docid026783 rev 2 31/58 STCH01 operation description 58 as a result of the energy delivery stop, the output voltage across the capacitor c out and the v dd voltage across the capacitor c aux decreases linearly, due to the consumption of the stwk01 and of the primary device respectively. referring to the time diagram in figure 15 the following relationship can be written: equation 16 where i cons_prim and i cons_sec represent the residual consumption at the primary and secondary side respectively. it is clear from the time diagram that the minimum voltage across the capacitor on the v dd pin has to be greater than the off threshold v dd_off (because the hv start-up generator is not active during the burst mode operation). this v dd supply voltage constraint has to be assured from an application design point of view, by a proper choice of c aux and of the number of turns n aux of the transformer auxiliary winding. figure 15. vout and vdd voltage drop during operation stop after detecting the wake-up signal on the zcd pin, all the internal blocks are reactivated; then the primary side controller refreshes the sample and hold voltage (lost during the long stop period), while keeping the comp in high impedance, and starts delivering low energy pulses at the controlled peak current (progressively increased): this prevents audible noise from the transformer. when the sampled and held voltage is well correlated to the output voltage, the control is passed again to the feedback loop, relying on the comp voltage information. after the output capacitor charge has been refreshed, if the load is not changed, the comp voltage will again decrease below the threshold v compbm with a consequent operation stop: in this way the converter will work in the burst mode until the load is increased. r x w f r q v v h f f r q v s u l p d x [ r x w ' ' ' ' f r q v v h f d x [ r x w f r q v s u l p r x w a 9 , , & & a 9 a 9 , & a 9 , & a 7 ? ? = => ? = ? = 6orsh ,frqvbvhf&rxw !9 ''brii 9rxw 9 '' 7 9rxw 9 '' 6orsh ,frqvbsulp&dx[ $0
operation description STCH01 32/58 docid026783 rev 2 figure 16 shows a block diagram of the burst mode entering and exiting logic. the wake-up pulse, in order to be correctly sensed on zcd pin, needs to have amplitude higher than the wake-up threshold v zcdwupth for a period longer than t wup_min . because after the last switching cycle before entering burst-mode a ringing takes place on the auxiliary winding of the transformer (and hence on the zvd pin as well), a false wake-up event could be triggered: to avoid this, a masking time t wup_mask is inserted (starting from the end of last transformer demagnetization) so that this ringing may fade up below the wake-up threshold v zcdwupth within t wup_mask figure 16. burst mode operation logic 9 &203%0 b 6wdqge\ /2*,& :dnhxs vhqvlqj &203 =&' 7rwxuqrq orjlf :dnhxs /2*,& 'hpdj 6dqg+ 7rwxuqrq orjlf ($ b )urpfxuuhqw vhqvhuhvlvwru &93:0 frpsdudwru $0
docid026783 rev 2 33/58 STCH01 operation description 58 8.10 burst mode operation (opto version) when the load decreases , the feedback loop reacts lowering the comp pin voltage. if it falls below the burst mode threshold, v compbm , the controller stops switching. then, as a result of the feedback reaction to the energy delivery stop, the comp voltage increases; when it exceeds the level, v compbm + hys, the power low-side mosfet starts switching again. the systems alternates period of time where the power mosfet is switching to the period of time where the power mosfet is not switching (burst mode operation: see figure 17 ). figure 17. burst mode timing diagram the power delivered to output during switching periods exceeds the load power demand; the excess of power is balanced from a not switching period, where no power is processed. the advantage of the burst mode operation is an average switching frequency much lower than the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. 8.11 frequency jitter for emi reduction in order to reduce the emi filtering, a proprietary frequency jitter technique is implemented in the controller, based on the injection of a modulating signal at 11 khz (above the feedback loop bandwidth) with a 50% duty cycle on the current sense signal: this signal is a square waveform that modulates the amplitude of the peak primary current. the percentage of this amplitude is set as a default at 5% and can be changed with online trimming by the user. as the peak current reduces with decreasing load levels, the effect of this modulation automatically attenuates at lower loads, where the energy of emi noise is highly reduced.
operation description STCH01 34/58 docid026783 rev 2 8.12 ovp function a dedicated ovp pin allows for overvoltage protection: through a resistive divider sensing the auxiliary winding, a sample of the output voltage is sensed and compared with the internal reference v ovp ; in case the threshold is surpassed, a latched protection trip occurs. the sampling of the sensed voltage is operated at the end of transformer demagnetization (contextually to the feedback sensing on zcd pin), where the sample is a representative value of the output voltage. by choosing the value of the low-side resistor of ovp divider (r ovp_l) , the high-side resistor (r ovp_h ) can be calculated as follows: equation 17 where v ovp is the internal voltage threshold of the ovp comparator and v out_pro t is the output voltage level where the protection will trigger. 8.13 hiccup mode ocp the device is also protected against a short-circuit of the secondary rectifier, short-circuit on the secondary winding or a hard saturation of the flyback transformer. a comparator monitors continuously the voltage on the r sense and activates a protection circuitry if this voltage exceeds the threshold v csdis . to distinguish an actual malfunction from a disturbance (e.g. induced during esd tests), the first time the comparator is tripped, the protection circuit enters a ?warning state?. if in the subsequent switching cycle the comparator is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; if the comparator will be tripped again a real malfunction is assumed and the device will be stopped. this condition is latched as long as the device is supplied. while it is disabled, however, no energy is coming from the self-supply circuit; hence the voltage on the v dd capacitor will decay and cross the off threshold v dd_off after some time, which clears the latch. the internal start-up generator is still off, then the v dd voltage still needs to go below its restart threshold v dd_restart before the capacitor on the v dd pin is charged again and the device restarted (at a reduced charging current i dd_ch ). ultimately, this will result in a low- frequency intermittent operation (hiccup mode operation), with very low stress on the power circuit. this special condition is illustrated in the timing diagram of figure 18 . 2 9 3 / 2 9 3 2 9 3 2 8 7 3 5 2 7 6 ( & $ 8 ; 2 9 3 + 5 9 9 9 1 1 5 ? ? ? =
docid026783 rev 2 35/58 STCH01 operation description 58 figure 18. hiccup mode ocp: timing diagram 8.14 generic protection pin (prot) the prot pin is the input pin for a user defined protection circuit (for example secondary side ovp or otp): if the voltage on the pin is kept below the v prot threshold, the device stops operating. the internal pull-up circuit keeps the pin voltage higher than the threshold without any external component. if the protection function is not used, the prot pin has to be left open. thanks to the stable current source capability of the prot pin, a thermal protection can be realized by simply connecting a ntc thermistor to the pin. this protection can be, according to the selected option, autorestart or latched type. figure 19. prot pin intervention timi ng diagram (autorestart bit option) '5$,1 9 ''brq 9 ''bri i 9 ''buhvwduw 6hfrqgdu\glrghlvvkruwhgkhuh w w w 9 5vqv 7zrvzlwfklqjf\fohv 9 '' 9fv glv $0 7 - 9 '' 89/2 9 ''brq 9 ''brii 7 6' 3urwhfwlrq rffxuuhqfh 3urwhfwlrq uhvhw &rqyhuwhu uhvwduw 9 '5$,1 7 +<67 9 ''buhvwduw $0
operation description STCH01 36/58 docid026783 rev 2 in the case of latch bit option, once the protection trips, a v dd on/off cycle is needed to attempt a new restart. in the autorestart bit option case, after protection trip, when the pin voltage increases above the shutdown threshold, the operation resumes at the first uvlo signal rising edge, as depicted in figure 19 . it is worth pointing out that in the autorestart case, the pin current capability is reduced after protection tripping, confirming in this way the protection occurrence and providing a current hysteresis to the protection logic, for a correct and safe operation. 8.15 thermal shutdown the thermal sensor is implemented inside the low-side mosfet device and senses its junction temperature; when this reaches the shutdown threshold t sd (typ. 150 c, min. 130 c), the controller stops the operation, allowing the mosfet cool down. the operation resumes when the junction temperature decreases of t hyst (typ. 30 c), at the next positive going edge of the uvlo signal, according to the autorestart procedure (see figure 20 ). figure 20. thermal shutdown timing diagram 9 3527 9 '' 89/2 9 ''brq 9 ''brii 9 3527b6' 3urwhfwlrq rffxuuhqfh 3urwhfwlrq uhvhw &rqyhuwhu uhvwduw 9 '5$,1 9 ''buhvwduw $0
docid026783 rev 2 37/58 STCH01 online trimming 58 9 online trimming 9.1 general features the embedded digital trimming allows the user to adjust and permanently store via software, all the parameters included in ta ble 7 during the production test of the end product, compensating the tolerance of the external components and the error due to their discretization values. the device provides a non-volatile memory (nvm) based on an otp (one-time- programmable memory) and a volatile memory. the volatile memory is used to adjust the value of all the parameters in table 7 : once the optimal values have been found the user can permanently store them in the otp memory. at device power-on, the parameter values depend on the otp status: ? if the ic has never been burnt (i.e. no value was permanently stored in otp memories), the parameters are initialized at default values (refer to ta ble 13 , tab le 15 , table 17 and ta ble 19 . ? if the ic was already burnt (i.e. values stored in the otp) the parameter values are the ones selected and stored by the user during the trimming process. the device is provided with an i 2 c slave only interface that requires only two pins for the communication: sda and scl. the i 2 c interface allows the user to access the device in a simple way, via the i 2 c -bus, assuring robust data communication integrity also thanks to an additional parity check control. two wires, sda and scl, carry information between the devices connected to the i 2 c bus. the device can operate only as i 2 c slave, i.e. it needs to be addressed by a master (a micro, industrial pc, ate, etc.) that initiates a data transfer on the bus and generates the scl signal to permit that transfer. generation of scl signals on the i 2 c bus is always the responsibility of the master. the device can operate as either a receiver or transmitter (transmitter-slave), depending on the command received from the master. serial sda and scl are bidirectional lines connected to a positive supply voltage via a pull- up resistor: the device has an internal pull-up on the pin sda and scl in order to pull high the pins when they are floating, but the user has to implement an adequate pull-up of the lines via external pull-up resistors. when the bus is free, both lines are high. table 7. adjustable parameter list parameter description v ref output voltage accuracy setting g i * v cref output current accuracy setting r ff voltage feed-forward accuracy setting ipk jitter amplitude option
online trimming STCH01 38/58 docid026783 rev 2 the data on the sda line must be stable during the high period of the scl. the high or low state of the sda line can only change when the scl signal on the scl line is low. within the procedure of the i 2 c bus, unique situations arise which are defined as start (s) and stop (p) conditions. a high to low transition on the sda line while scl is high is one such unique case. this situation indicates a start condition. a low to high transition on the sda line while the scl line is high defines a stop condition. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus stays busy if a repeated start (sr) is generated instead of a stop condition. in this respect, the start (s) and repeated start (sr) conditions are functionally identical. every byte put on the sda line is 8 bits long. each byte is followed by an acknowledge bit. data is transferred with the most significant bit (msb) first. data transfer with acknowledge is obligatory. the acknowledge related scl pulse is generated by the master. the transmitter releases the sda line (high) during the acknowledge scl pulse. the receiver pulls down the sda line during the acknowledge scl pulse so that it remains stable low during the high period of this scl pulse. of course, setup and hold time must also be taken into account. when the device is addressed, it generates an acknowledge after the address byte has been received. when the device doesn't acknowledge the address, the sda line is left high by the device. the master can then generate either a stop condition to abort the transfer, or a repeated start condition to start a new transfer. if a device receiver does acknowledge the address but, sometime later in the transfer cannot receive any more data bytes, the master must again abort the transfer. this is indicated by the device generating the not acknowledge on the bytes to follow. the device leaves the sda line high and the master generates a stop or a repeated start condition. if a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. the slave transmitter must release the sda line to allow the master to generate a stop or repeated start condition. data transfers have the following format: after the start condition (s), a slave address is sent. this address is 7 bits long followed by an eight bit which is a data direction bit (r/w) - a ?zero? indicates a transmission (write), a ?one? indicates a request for data (read). a data transfer is always terminated by a stop condition (p) generated by the master. however, if a master
docid026783 rev 2 39/58 STCH01 online trimming 58 still wishes to communicate on the bus, it can generate a repeated start condition (sr) and address the slave without first generating a stop condition. 9.2 device address the device is provided with the following fixed 7-bit address (corresponding to < 58 > hex), while the 8 th bit is the data direction (r/w): 9.3 device commands the commands are implemented with one byte word including a bit for a parity check (lsb): the parity check on bit c0 has the following structure: c0 = c7 c6 c5 c4 c3 c2 c1,( is the xor operator) the possible commands are summarized in ta ble 10 : if the device receives a command not specified in this table or in case of a parity check failure, no command is executed and a fail flag is internally activated. table 8. device address register msb lsb a6 a5 a4 a3 a2 a1 a0 r/w 1 0 1 1 0 0 01/0 table 9. device commands register msb lsb c7 c6 c5 c4 c3 c2 c1 c0 table 10. command mapping ( c0 = parity check bit) command code c7 c6 c5 c4 c3 c2 c1 c0 emulate/read v ref 00010010 emulate/read g i * v cref 11000011 emulate/read r ff 10011010 emulate/read ipk 01010011 reset volatile memory to default 11010111 write nvm 01010101
online trimming STCH01 40/58 docid026783 rev 2 data strings the data are implemented with one byte word including a bit for a parity check (lsb). the parity check on bit d0 has the following structure: d0 = d7 d6 d5 d4 d3 d2 d1,( is the xor operator) in case the parity bit check is not correct the data is not acquired, the parameter value (depending on the command) will be not updated: an internal parity fail flag is activated and it is no possible to execute any command before a read command. 9.4 emulation commands it is possible to change all adjustable parameter values writing the volatile memory (in the various parameter registers) before deciding to permanently store the values in the device. the user is only allowed to toggle default bit value per each bit in each parameter once. thus after a toggle 0 1 (or 1 0) of the generic parameter bit, to revert it to its default value a reset operation is needed as described further ahead. the change of each parameter is done in independent way. table 11. data strings register msb lsb d7 d6 d5 d4 d3 d2 d1 d0
docid026783 rev 2 41/58 STCH01 online trimming 58 9.5 emulate v ref the emulate v ref command writes data in the volatile v ref instruction: it is a write type command and corresponds to the code reported in table 12: emulate v ref instruction : the value of v ref is changed according to the data sent (see ta ble 13 ). lsb is the parity check bit. table 12. emulate v ref instruction start /stop byte1 (address, write type) ack byte2: command ack byte3: write data ack start /stop emulate v ref s a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 1 0 0 1 0 0 0 0 v ref 5 data bits pck 0 p x x sent by slave (device) x x x sent by master table 13. v ref values data bits trim step [%] v ref value [v] d4 d3 d2 d1 d0 10000 -9.6% 2.260 10001 -9.0% 2.275 10010 -8.4% 2.290 10011 -7.8% 2.305 10100 -7.2% 2.320 10101 -6.6% 2.335 10110 -6.0% 2.350 10111 -5.4% 2.365 11000 -4.8% 2.380 11001 -4.2% 2.395 11010 -3.6% 2.410 11011 -3.0% 2.425 11100 -2.4% 2.440 11101 -1.8% 2.455 11110 -1.2% 2.470 11111 -0.6% 2.485 0 0 0 0 0 0.0% 2.500 default (1) , (2) 0 0 0 0 1 0.6% 2.515 0 0 0 1 0 1.2% 2.530 0 0 0 1 1 1.8% 2.545
online trimming STCH01 42/58 docid026783 rev 2 in case of a parity check fail (command or data) the command is not executed ( v ref register doesn't change) and an internal parity fail flag is activated: if the parity fail flag is activated from the previous communication, the command is not executed even if the parity check is ok; the parity fail flag is reset by the first read command. if the parity check is ok, the v ref is changed accordantly to the v ref register content with a direct change from the old to the new value. 0 0 1 0 0 2.4% 2.560 0 0 1 0 1 3.0% 2.575 0 0 1 1 0 3.6% 2.590 0 0 1 1 1 4.2% 2.605 0 1 0 0 0 4.8% 2.620 0 1 0 0 1 5.4% 2.635 0 1 0 1 0 6.0% 2.650 0 1 0 1 1 6.6% 2.665 0 1 1 0 0 7.2% 2.680 0 1 1 0 1 7.8% 2.695 0 1 1 1 0 8.4% 2.710 0 1 1 1 1 9.0% 2.725 1. please note: the device is initia lized with the default value of 00000 (i.e. the 0% trim value for v ref ); in case the device is already burnt, the default value is the one stored in the otp. 2. please note: the 0% trim value was assumed 2.5 v as an ex ample but this value can be in the range [2.48 v, 2.52 v]. the trimming range is proportional to the trimming value [-9.6%, + 9%] with a trimming step of 0.6% referred to the 0% trim value. table 13. v ref values (continued) data bits trim step [%] v ref value [v] d4 d3 d2 d1 d0
docid026783 rev 2 43/58 STCH01 online trimming 58 9.6 emulate g i * v cref the emulate g i * v cref command writes data in the volatile g i * v cref instruction: it is a write type command and corresponds to the code reported in table 14: emulate gi * vcref instruction . the value of g i * v cref is changed according to the data sent (see table 15 ). lsb is the parity check bit. table 14. emulate g i * v cref instruction start/stop byte1 (address, write type) ack byte2: command ack byte3: write data ack start/stop emulate g i * v cref s a6 a5 a4 a3 a2 a1 a0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 g i * vc ref 4 data bits pck 0 p x x sent by slave (device) x x x sent by master table 15. g i * v cref values data bits trim step [%] g i * v cref value [mv] d3 d2 d1 d0 1000 -12.0% 0.176 1001 -10.5% 0.179 1010 -9.0% 0.182 1011 -7.5% 0.185 1100 -6.0% 0.188 1101 -4.5% 0.191 1110 -3.0% 0.194 1111 -1.5% 0.197 0000 0.0% 0.200 default (1) , (2) 0001 1.5% 0.203 0010 3.0% 0.206 0011 4.5% 0.209 0100 6.0% 0.212 0101 7.5% 0.215
online trimming STCH01 44/58 docid026783 rev 2 in case of a parity check fail (command or data) the command is not executed ( g i * v cref register doesn't change) and an internal parity fail flag is activated: if the parity fail flag is activated from the previous communication, the command is not executed even if the parity check is ok; the parity fail flag is reset by the first read command. if a parity check is ok, the g i * v cref is changed accordantly to the g i * v cref register content with a direct change from the old to the new value. 0110 9.0% 0.218 0111 10.5% 0.221 1. please note: the device is initialized with the default value of 0000 (i.e. 0% trim value of g i * v cref ); in case the device is already burnt, the default value is the one stored in the otp. 2. please note: the 0% trim value was assumed 0.2 v as an exam ple but this value can be in the range [0.19 v, 0.21 v]. the trimming range is proportional to the trimming value [-12% ; + 10.5%] with a trimming step of 1.5% referred to the 0% trim value. table 15. g i * v cref values (continued) data bits trim step [%] g i * v cref value [mv] d3 d2 d1 d0
docid026783 rev 2 45/58 STCH01 online trimming 58 9.7 emulate r ff the emulate r ff command writes data in the volatile r ff instruction: it is a write type command and corresponds to the code reported in ta ble 16 . the value of r ff is changed according to the data sent (see tab le 17 ). lsb is the parity check bit. table 16. emulate r ff instruction start/stop byte1 (address, write type) ack byte2: command ack byte3: write data ack start/stop emulate r ff s a6 a5 a4 a3 a2 a1 a0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 r ff 4 data bits pck 0 p x x sent by slave (device) x x x sent by master table 17. r ff values data bits trim step [%] r ff value [ ] d3 d2 d1 d0 1000-20% 48.00 1 0 0 1 -17.5% 49.50 1010-15% 51.00 1 0 1 1 -12.5% 52.50 1100-10% 54.00 1101-7.5% 55.50 1110 -5% 57.00 1111-2.5% 58.50 0 0 0 0 0% 60.00 default (1)(2) 00012.5% 61.50 0010 5% 63.00 00117.5% 64.50 0100 10% 66.00 0 1 0 1 12.5% 67.50
online trimming STCH01 46/58 docid026783 rev 2 in case of a parity check fail (command or data) the command is not executed ( r ff register doesn't change) and an internal parity fail flag is activated: if the parity fail flag is activated from the previous communication, the command is not executed even if the parity check is ok; the parity fail flag is reset by the first read command. if the parity check is ok, the r ff is changed accordantly to the r ff register content with a direct change from the old to the new value. 0110 15% 69.00 0 1 1 1 17.5% 70.50 1. please note: the device is init ialized with the default value of 0000 (i.e. 0% trim value of r ff ); in case the device is already burnt, the default value is the one stored in the otp. 2. please note: the 0% trim value was assumed 25 as an example but this value can be in the range [54 , 66 ]. the trimming range is proportional to the trimming value [-20% + 17.5%] with a trimming step of 2.5% referred to the 0% trim value. table 17. r ff values (continued) data bits trim step [%] r ff value [ ] d3 d2 d1 d0
docid026783 rev 2 47/58 STCH01 online trimming 58 9.8 emulate ipk the emulate ipk command writes data in the volatile ipk instruction: it is a write type command and corresponds to the code reported in ta ble 18 . the value of ipk is changed according to the data sent (see table 19 ). lsb is the parity check bit. in case of a parity check fail (command or data) the command is not executed ( ipk register doesn't change) and an internal parity fail flag is activated: if the parity fail flag is activated from the previous communication, the command is not executed even if the parity check is ok; the parity fail flag is reset by the first read command. if the parity check is ok, the ipk is changed accordantly to the ipk register content with a direct change from the old to the new value. table 18. emulate ipk instruction start/stop byte1 (address, write type) ack byte2: command ack byte3: write data ack start/stop emulate ipk s a6 a5 a4 a3 a2 a1 a0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 ipk3 data bits pck 0 p x x sent by slave (device) x x x sent by master table 19. ipk values data bits ipk% value d2 d1 d0 0 1 1 0% (no jitter) 0103% 0014% 0 0 0 5% default (1) 1116.5% 1108% 10110% 10012% 1. please note: the device is init ialized with the default value of 000 (i.e. 5% trim value of ipk); in case the device is already burnt, the default value is the one stored in the otp.
online trimming STCH01 48/58 docid026783 rev 2 9.9 read commands it is possible to read the content of the volatile memory and also the status of the nvm memory that indicates if the nvm is virgin or burnt, or if an error occurred during the trimming process ( status register ) (see ta ble 20 ). the reading command of the volatile memory can be used to check the value written in the volatile memory before to permanently store it, increasing the robustness of trimming process; as described in section 9.4: emulation commands on page 40 , the reading of the non-volatile memory is necessary to reset the internal parity fail flag eventually activated by a communication error during the trimming process. 9.9.1 read v ref the command read v ref command reads data of the volatile v ref register and the otp status register : it is a write/read type command and corresponds to the code reported in ta ble 21 . once the device receives the command emulate/read v ref , in order to perform a reading it is necessary to send a repeated start (sr) and address as read type, i.e. with the lsb (r/w) set at ?one?; the device will send on the sda line an 8-bit word, where the first two bits are the status register bit m1 and m0 and the following 6 bits are the value of v ref with a parity check as lsb. in case of a communication error the content of the status register is <11>, and it means that the internal parity flag fail is activated: after a reading command is executed, the parity flag fail is reset and a new command can be executed by the device. table 20. status register status register description value m1 nvm write residual possibility 0 1 otp not yet programmed otp programmed m0 parity fail flag 0 1 parity success parity failed table 21. read v ref instruction start/stop byte1 (address, write type) ack byte2: command ack start/stop byte3 (address, read type) ack byte 4: read data nack start/stop read v ref s a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 0 0 0 0 1 0 0 1 0 0 sr a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 0 m 1 m 0 v ref 5 data bits pck 1 p x x sent by slave (device) x x x sent by master
docid026783 rev 2 49/58 STCH01 online trimming 58 9.9.2 read g i * v cref the command read g i * v cref command reads data of the volatile g i * v cref register and the otp status register : it is a write/read type command and corresponds to the code reported in table 22 . once the device receives the command emulate/read g i * v cref , in order to perform a reading it is necessary to send a repeated start (sr) and address as read type, i.e. with the lsb (r/w) set at ?one?; the device will send on the sda line an 8-bit word, where the first two bits are the status register bit m1 and m0 and the following 6 bits are the value of v ref with a parity check as lsb. in case of a communication error the content of the status register is <11>, and it means that the internal parity flag fail is activated: after a reading command is executed, the parity flag fail is reset and a new command can be executed by the device. table 22. read g i * v cref instruction start/stop byte1 (address, write type) ack byte2: command ack start/stop byte3 (address, read type) ack byte 4: read data nack start/stop read g i * v cref s a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 0 1 1 0 0 0 0 1 1 0 s r a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 0 m 1 m 0 0 g i * v cref 4 data bits pck 1 p x x sent by slave (device) x x x sent by master
online trimming STCH01 50/58 docid026783 rev 2 9.9.3 read r ff the command read r ff command reads data of the volatile r ff register and the otp status register : it is a write/read type command and corresponds to the code reported in ta ble 23 . once the device receives the command emulate/read r ff , in order to perform a reading it is necessary to send a repeated start (sr) and address as read type, i.e. with the lsb (r/w) set at ?one?; the device will send on the sda line bus an 8-bit word, where the first two bits are the status register bit m1 and m0 and the following 6 bits are the value of r ff with a parity check as lsb. in case of a communication error the content of the status register is <11>, and it means that the internal parity flag fail is activated: after a reading command is executed, the parity flag fail is reset and a new command can be executed by the device. table 23. read r ff instruction start/stop byte1 (address, write type) ack byte2: command ack start/stop byte3 (address, read type) ack byte 4: read data nack start/stop read r ff s a 6 a 5 a 4 a 3 a2 a 1 a 0 0 0 1 0 0 1 1 0 1 0 0 s r a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 0 m 1 m 0 0 r ff 4 data bits pck 1 p x x sent by slave (device) x x x sent by master
docid026783 rev 2 51/58 STCH01 online trimming 58 9.9.4 read ipk the command read ipk command reads data of the volatile ipk register and the otp status register : it is a write/read type command and corresponds to the code reported in ta ble 24 . once the device receives the command emulate/read ipk, in order to perform a reading it is necessary to send a repeated start (sr) and address as read type, i.e. with the lsb (r/w) set at ?one?; the device will send on the sda line bus an 8-bit word, where the first two bits are the status register bit m1 and m0 and the following 6 bits are the value of ipk with a parity check as lsb. in case of a communication error the content of the status register is <11>, and it means that the internal parity flag fail is activated: after a reading command is executed, the parity flag fail is reset and a new command can be executed by the device. 9.10 reset command it is possible to reset all adjustable parameter values written in the volatile memory (in the various parameter registers). the reset command acts on all parameters simultaneously. 9.11 reset volatile memory the reset volatile memory command resets data in the volatile registers : it is a write type command and corresponds to the code reported in ta ble 25 : table 24. read ipk instruction start/stop byte1 (address, write type) ack byte2: command ack start/stop byte3 (address, read type) ack byte 4: read data nack start/stop read ipk s a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 0 0 1 0 1 0 0 1 1 0 s r a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 0 m 1 m 0 0 0 ipk 3 data bits pck 1 p x x sent by slave (device) x x x sent by master
online trimming STCH01 52/58 docid026783 rev 2 9.12 write nvm (otp) after the various parameters have been trimmed to the desired level, the user can confirm their values and store them permanently. this is a virtually real-time trim-and-test without switching off the supply. it is important that during all the process the supply voltage of the ic never falls below its uvlo level, otherwise, the settings stored in the volatile memory will be lost and the ic comes back to the default setting; it is also necessary that the burnt instruction is executed with a v dd = 19 v with a current capability of 90 ma. in case that the research of the best parameter value is done with a v dd value lower than 19 v, the user has to pay attention that during the step-up of v dd before the burning of the nvm a negative ringing on v dd will cause a drop below the uvlo of the ic. the user can eventually decide to perform the research of the best parameter value, store these values in an external memory (ate, industrial pc, etc.), then increase the v dd to 19 v wait to have a stable v dd level and send again the selected parameter values stored in the external memory before to send the burn nvm command. all the values written in the various parameter registers (volatile memory) are permanently stored into the nvm (otp) in a single step. sending the burnt command reported (write type) in ta ble 26 followed a data byte with the same codification of burn command, it is possible burn the nvm. it is important to provide a zapping time of at least 45 msec and to have the v dd = 19 v of the ic, with a current capability of 90 ma, in order to ensure a correct blowing of the antifuse cells. to protect the nvm memory from wrong writing, if the parity fail flag is activated, i.e. an error occurred during the trimming process, the burn command is not executed. table 25. reset volatile memory instruction start/ stop byte1 (address, write type) ack byte2: command ack start/ stop emulate v ref s a6 a5 a4 a3 a2 a1 a0 00 1 1 0 1 0 1 1 1 0 p x x sent by slave (device) x x x sent by master table 26. write nvm (otp) instruction start/stop byte1 (address, write type) ack byte2: command ack byte3 (data) ack start/stop write nvm s a6 a5 a4 a3 a2 a1 a0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 p x x sent by slave (device) x x x sent by master
docid026783 rev 2 53/58 STCH01 online trimming 58 after the stop (p) the device doesn't acknowledge any i 2 c communication for about 45 ms in order to perform the burning of the nvm. please note that after a write nvm command the status register is not automatically updated. it must be updated by turning off and on again the ic. once the update is performed, the i 2 c bus is no more available.
online trimming STCH01 54/58 docid026783 rev 2 9.13 multiplexed scl and sda inputs the scl and sda inputs are multiplexed with ovp and prot functionalities respectively; for this reason, before the online trimming procedure, the ovp and prot functions are not active; only after the online trimming procedure, when all internal parameters have been fixed and stored in the non-volatile-memory, the ovp and prot functions are activated. after the online trimming process is over, further access through the i 2 c bus is not any longer allowed and consequently the internal non-volatile-memory cannot be accessible for reading.
docid026783 rev 2 55/58 STCH01 package information 58 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. figure 21. so16n package outline 621
package information STCH01 56/58 docid026783 rev 2 table 27. so16n package mechanical data symbol dimensions (mm) min. typ. max. notes a 1.75 a1 0.10 0.25 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 9.80 9.90 10.00 (1) , (2) 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both side s ). 2. dimensions referred to the bottom side of the package. e 5.80 6.00 6.20 e1 3.80 3.90 4.00 (3) , (2) 3. dimension ?e1? does not include interlead flash or pr otrusions. interlead flash or protrusions shall not exceed 0.25 mm per side. e 1.27 h 0.25 0.50 l 0.40 1.27 k 0 8 degrees ccc 0.10
docid026783 rev 2 57/58 STCH01 revision history 58 11 revision history table 28. document revision history date revision changes 06-aug-2014 1 initial release. 08-aug-2014 2 updated title, features and description in cover page. updated table 1: device summary . inserted table 3: typical power . minor text changes.
STCH01 58/58 docid026783 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of STCH01

	To Download STCH01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .